Published in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026
An FPGA-ASIC co-design framework that decomposes large-scale Ising/QUBO problems in hardware so that fixed-capacity physics-based Ising chips can solve problems far larger than a single die can hold.
Published in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026
A study of how well Ising machines handle structured, circuit-derived SAT instances, identifying where physics-based solvers hit their limits on these workloads.
Published in ACM/IEEE International Symposium on Computer Architecture (ISCA), 2026
An optimizing compiler that maps SAT instances onto Ising hardware, enabling physics-based Ising machines to tackle satisfiability problems at scale.
Published in IEEE/ACM Design, Automation and Test in Europe (DATE), 2026
FLAME explores mapping and scheduling strategies for multi-cycle operations on CGRAs, addressing the tension between pipeline depth, resource utilization, and throughput in reconfigurable computing fabrics.
Published in ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2026
A unified compilation and architecture framework for coarse-grained reconfigurable arrays (CGRAs) that introduces hierarchical spatio-temporal scheduling to improve tile utilization and performance portability.
Published in Scientific Reports, 2026
Uses a 28nm coupled-oscillator CMOS Ising chip as a physical entropy source for hybrid true random number generation, targeting probabilistic compute applications. (Co-first author)
Published in IEEE Access, vol. 14, 2026
Demonstrates that extractive text summarization can be formulated as a QUBO instance and solved on a CMOS Ising machine, showcasing a practical NLP application for physics-based computing hardware.
Published in IEEE European Solid-State Electronics Research Conference (ESSERC), 2025
A silicon Ising chip featuring a fully-connected annealing core, an on-chip Hamiltonian engine, and an integrated RISC-V processor for gradient-guided search, enabling solution of combinatorial optimization problems with 2,500+ spins.